A continuing goal of the semiconductor industry has been to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND Flash memory devices). One way of increasing memory density in non-volatile memory devices is to utilize architectures including an array of vertical memory cells (also referred to as “three-dimensional (3D) memory devices”). A conventional array of vertical memory cells includes semiconductor pillars as channels extending through openings in a stack of alternating conductive gate materials (e.g., word lines, control gates, access lines) and dielectric materials at each junction of the semiconductor pillars and the conductive structures. The vertical memory cells define a vertical memory string along each pillar. Such a configuration permits a greater number of memory cells to be located in a given unit of die surface area by building the array upwards (e.g., vertically) on a die, as compared to structures with conventional planar (e.g., two-dimensional) arrangements of cells.
An example of an array of vertical memory cells is a so-called “MONOS”-type memory array, which stands for metal-oxide-nitride-oxide-semiconductor, referring to the materials forming each individual vertical memory cell. Conventional MONOS-type memory arrays may be formed by forming the semiconductor pillars through a stack of alternating first and second dielectric materials, forming openings through the stack adjacent to the semiconductor pillars, removing the first dielectric materials through the openings, and replacing the first dielectric materials with a conductive material to form word line elements. During such a process, all or substantially all of the first dielectric material is replaced by the conductive material, such that a body of the vertical memory array includes alternating layers of the second dielectric material and the conductive gate materials. The semiconductor pillars function as a channel material for the vertical memory cells.
As technology advances in 3D memory devices, arrays of vertical memory cells are being produced and designed with an increased number of alternating conductive gate materials and dielectric materials to increase a number of transistors. This increase results in a stack with a greater height, and vertical memory strings also have an increased length in order to pass through the stack with the greater height. The semiconductor pillars (e.g., channel materials) in the longer vertical memory strings may need to carry an increased current to effectively operate all the vertical memory devices in a vertical memory string. Conventional polycrystalline silicon (also known as “polysilicon”) exhibits a substantial number of defects and traps in the channels, and is also very sensitive to high operation temperatures, such as from 50° C. to 150° C. Polysilcon used in semiconductor channels exhibits an electron mobility of about 10 cm2/(V·s) and a room temperature band gap of about 1.12 eV, which may not be sufficient to reliably and effectively operate all vertical memory devices in a vertical memory string having an increased length. Moreover, polysilicon channel materials may result in an insufficient gate-induced drain leakage (“GIDL”) current for erase functions on such long vertical memory strings. Accordingly, polysilicon channel materials may not be suitable for use with an increasing number of stacked transistors.